? ? high? speed? cmos ? logic? ? ? 54HC14 ? hex schmitt-trigger inverter logic ic in bare die form ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? die size (unsawn) 1250 x 1250 49 x 49 m mils minimum bond pad size 100 x 100 3.94 x 3.94 m mils die thickness 350 (20) 13.78 (0.79) m mils top metal composition al 1%si 1.1m back metal composition n/a C bare si ? output drive capability: 10 lsttl loads ? low input current: 1a ? outputs directly inter face cmos, nmos and ttl ? operating voltage range: 2v to 6v ? cmos high noise immunity ? function compatible with 54ls14 ? full military temperature range. rev 1.0 24/11/17 features: ordering information description the 54HC14 hex schmitt-trigger inverter is fabricated using a 2.5m 5v cmos proce ss with the same high speed performance of lsttl combined with cmos low power consumption. the device performs the boolean function y = ? in positive logic. device inputs are compatible with standard cmos outputs; with pull-up resistors, they are compatible with lsttl output s. schmitt-trigger inputs transform slow input rise and fall times into sharply defined jitter-free output signals. due to the hysteresis voltage of the schmitt trigger, the 54HC14 is useful in noisy environments. die dimensions in m (mils) the following part suffixes apply: 1250 (49) ? no suffix - mil-std-883 /2010b visual inspection ? h - mil-std-883 /2010b visual inspection + mil-prf-38534 class h lat 1250 (49) ? k - mil-std-883 /2010a visual inspection (space) + mil-prf-38534 class k lat lat = lot acceptance test. for further information on la t process flows see below. www.siliconsupplies. com\quality\bare-die-lot-qualification supply formats: mechanical specification ? default C die in waffle pack (400 per tray capacity) ? sawn wafer on tape C on request ? unsawn wafer C on request ? die thickness <> 350m(14 mils) C on request ? assembled into ceramic package C on request page ? 1 ? of ? 5 ? www.siliconsupplies.com a l l d a t a s h e e t . c o m
page ? 2 ? of ? 5 ? www.siliconsupplies.com ? d? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? high? speed? cmos ? logic? ? ? 54HC14 rev 1.0 24/11/17 coordinates (mm) pad functio n x y 1 1a 0.14 0.345 2 1y 0 .14 0.141 3 2a 0.319 0.141 4 2y 0.577 0.141 5 3a 0.817 0.141 6 3y 1.019 0.141 7 gnd 1.036 0.47 8 4y 1.036 0.749 9 4a 1.006 1.007 10 5y 0.8 1.007 11 5a 0.584 1.007 12 6y 0.334 1.007 13 6a 0.141 0.969 14 v cc 0.14 0.663 connect chip back to v cc or float pad layout and functions logic diagram 1250m (49.21 mils) 1250m (49.21 mils) 0,0 13 14 1 2 3 4 5 6 7 8 9 10 11 12 die id function table inputs a output y l h h l h = high level (steady state) l ? = ? low ? level? (steady ? state) ? p ad 14 = v cc pad 7 = gnd y = ? ? a l l d a t a s h e e t . c o m
page ? 3 ? of ? 5 ? www.siliconsupplies.com ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? high? speed? cmos ? logic? ? ? 54HC14 rev 1.0 24/11/17 parameter symbol min max units supply voltage v cc 2 6 v dc input or output voltage v in ,v out 0 v cc v operating temperature range t j -55 +125 c v cc = 2.0v v cc = 4.5v input rise or fall times t r , t f v cc = 6.0v - no limit* ns * when v in = 50% v cc , i cc > 1ma. recommended operating conditions 3 (voltages referenced to gnd) absolute maximum ratings 1 parameter symbol value unit dc supply voltage (referenced to gnd) v cc -0.5 to +7.0 v dc input voltage (referenced to gnd) v in -0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out -0.5 to v cc +0.5 v dc input current i in 20 ma dc output current, per pad i out 25 ma dc supply current, v cc or gnd, per pad i cc 50 ma power dissipation in still air 2 p d 750 mw storage temperature range t stg -65 to 150 c 3. ? this device contains protecti on circuitry to guard against dama ge due to high static voltages or electric fields. however, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either gnd or v cc ). unused outputs must be left open. limits parameter symbol v cc conditions 25c 85c full range 4 units 2.0v 1.50 1.50 1.50 3.0v 2.15 2.15 2.15 4.5v 3.15 3.15 3.15 maximum positive- going input threshold voltage v t+ max 6.0v v out = 0.1v i out 20a 4.20 4.20 4.20 v 2.0v 1.0 0.95 0.95 3.0v 1.5 1.45 1.45 4.5v 2.3 2.25 2.25 minimum positive- going input threshold voltage v t+ min 6.0v v out = 0.1v i out 20a 3.0 2.95 2.95 v 2.0v 0.9 0.95 0.95 3.0v 1.4 1.45 1.45 4.5v 2.0 2.05 2.05 maximum negative-going input threshold voltage v t- max 6.0v v out = v cc -0.1v i out 20a 2.6 2.65 2.65 v dc electrical characteristics (voltages referenced to gnd) 1. ? operation above the absolute maxi mum rating may cause device fa ilure. operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. measured in plastic dip package , results in die form are dependent on die attach and assembly method. a l l d a t a s h e e t . c o m
page ? 4 ? of ? 5 ? www.siliconsupplies.com ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dc electrical characteristics continued (voltages referenced to gnd) high? speed? cmos ? logic? ? ? 54HC14 rev 1.0 24/11/17 limits parameter symbol v cc conditions 25c 85c full range 4 units 2.0v 0.3 0.3 0.3 3.0v 0.5 0.5 0.5 4.5v 0.9 0.9 0.9 minimum negative- going input threshold voltage v t- min 6.0v v out = v cc -0.1v i out 20a 1.2 1.2 1.2 v 2.0v 1.20 1.20 1.20 3.0v 1.65 1.65 1.65 4.5v 2.25 2.25 2.25 maximum hysteresis voltage 4 v h max 6.0v v out = 0.1v or v cc -0.1v i out 20a 3.00 3.00 3.00 v 2.0v 0.20 0.20 0.20 3.0v 0.25 0.25 0.25 4.5v 0.40 0.40 0.40 minimum hysteresis voltage 3 v h min 6.0v v out = 0.1v or v cc -0.1v i out 20a 0.50 0.50 0.50 v 2.0v 1.9 1.9 1.9 4.5v 4.4 4.4 4.4 6.0v v in v t- min i out 20a 5.9 5.9 5.9 v 3.0v v in v t- min i out 2.4ma 2.48 2.34 2.20 v 4.5v v in v t- min i out 4.0ma 3.98 3.84 3.70 v minimum high-level output voltage v oh 6.0v v in v t- min i out 5.2ma 5.48 5.34 5.20 v 2.0v 0.1 0.1 0.1 4.5v 0.1 0.1 0.1 6.0v v in v t+ max i out 20a 0.1 0.1 0.1 v 3.0 v in v t+ max i out 2.4ma 0.26 0.33 0.4 v 4.5v v in v t+ max i out 4.0ma 0.26 0.33 0.4 v maximum low-level output voltage v ol 6.0v v in v t+ max i out 5.2ma 0.26 0.33 0.4 v maximum input leakage current i in 6.0v v in = v cc or gnd 0.1 1.0 1.0 a maximum quiescent supply current i cc 6.0v v in = v cc or gnd, i out = 0a 1.0 10 40 a ? 4. -55?c t j +125?c 5. ?v h min > (v t+ min ) - (v t- max ); v h max = (v t+ max )+(v t- min ) a l l d a t a s h e e t . c o m
page ? 5 ? of ? 5 ? www.siliconsupplies.com ? ? high? speed? cmos ? logic? ? ? 54HC14 rev 1.0 24/11/17 ? a c electrical characteristics 6 limits ? parameter ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? disclaimer: the information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. with re spect to any examples or hints given herei n, any typical values stated h erein and/or any information r egarding the application of the d evice, silicon supplies ltd hereby disclaims any and all warranties and liabilities of any kind. life support policy : silicon supplies ltd components may be used in life support dev ices or systems only with the express written approval of silicon supplies ltd, if a failure of such componen ts can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted i n the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. symbol v cc conditions units full range 4 25c 85c 2.0v 75 95 110 3.0v 30 40 55 4.5v 15 19 22 maximum propagation c l = 50pf, delay, input a or b to output y (figure 1) t plh, t phl ns t r = t f = 6ns 6.0v 13 16 19 2.0v 75 95 110 3.0v 27 32 36 4.5v 15 19 22 maximum transition c l = 50pf, time, any output (figure 1) t tlh, t thl ns t r = t f = 6ns 6.0v 13 16 19 maximum input capacitance c in - - 10 10 10 pf typical power dissipation t j = 25c, v cc pf capacitance 7 c pd - = 5.0v 22 ? 6 . not production tested in die fo rm, characterized by chip desi gn and tested in package lat. 7. used to determine the no-load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . switching waveform dut c l * ? ? output test point test circuit * includes all probe and jig capacitance figure 1 C propagation ? delay,? transition ? timing a l l d a t a s h e e t . c o m
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